トップレベルのブロック分けが終了したのでRTL記述の段階に入る。

Signature Analyzerの時のようにQuartus IIでtemplateを使ってRTLスケルトンを入力してコンパイル。

top.v: topモジュール

module top(fin, ios1, ios2, xt1, xt2, a, b, hourset, s1, s2, s3, s4, dimmer, timeroutoff, blanking, ac, t1, t2, t3,
stopwatch, ambcout, pmfmout, sega, segb, segc, segd, sege, segf, segg, point, io, signalout, timerout, sleepout);

// Input Port(s)
input fin, ios1, ios2, xt1, a, b, hourset, s1, s2, s3, s4, dimmer, timeroutoff, blanking, ac, t1, t2, t3;

// Output Port(s)
output stopwatch, ambcout, pmfmout, sega, segb, segc, segd, sege, segf, segg, point, signalout, timerout, sleepout;
output [4:0] io;

// Inout Port(s)
output xt2;

// Parameter Declaration(s)

// Additional Module Item(s)
// A net models connectivity in a design.

// Scalar net
wire ce, reset, preset, load;
wire c3200hz, c800hz, c10hz, c1hz;
wire duty, strobe, timmadj, timhadj;
wire oncmpout, offcmpout, sleep;

// Unsigned vector
wire [19:0] fcounter;
wire [2:0] cs;
wire [16:0] clcounter, ontimer, offtimer, sleeptimer;

// Nets may be declared with many different types with different
// electrical characteristics:

// wire/tri Basic connection w/ typical electrical behavior

// supply1/supply0 Tied to VCC/GND

// tri1/tri0 Default to 1/0 if left undriven

// wor/trior Multiple drivers resolved by OR

// wand/triand Multiple drivers resolved by AND

// Basic module instantiation
fc fc(ac, fin, ce, reset, preset, load, fcounter);

cd cd(ac, xt1, xt2, c3200hz, c800hz, c10hz, c1hz);

control control(a, b, dimmer, ac, c800hz, c10hz,
ce, reset, preset, load, duty, strobe, timmadj, timhadj);

ct ct(ac, {s3,s2,s1}, timmadj, timhadj, c10hz, c1hz,
clcounter, ontimer, offtimer, sleeptimer, oncmpout, offcmpout, sleep);

disp disp(c3200hz, {s3,s2,s1}, fcounter, clcounter, ontimer, offtimer, sleeptimer,
oncmpout, offcmpout, sleep, duty, strobe, ac, blanking,
stopwatch, ambcout, pmfmout, sega, segb, segc, segd, sege, segf, segg, point,
io, signalout, timerout, sleepout);

endmodule


fc.v: FREQUENCY COUNTERモジュール

module fc(fin, ce, reset, preset, load, fcounter);

// Input Port(s)
input fin, ce, reset, preset, load;

// Output Port(s)
output reg [19:0] fcounter;

// Inout Port(s)

// Parameter Declaration(s)

// Additional Module Item(s)

endmodule

cd.v: CLOCK DIVIDERモジュール

module cd(xt1, xt2, c3200hz, c800hz, c10hz, c1hz);

// Input Port(s)
input xt1;

// Output Port(s)
output xt2, c3200hz, c800hz, c10hz, c1hz;

// Inout Port(s)

// Parameter Declaration(s)

// Additional Module Item(s)

endmodule

control.v: CONTROLモジュール

module control(a, b, hourset, s1, s2, s3, s4, dimmer, timeroutoff, blanking, ac, c800hz, c10hz,
ce, reset, preset, load, duty, strobe, blankingout, acout, cs, timmadj, timhadj);

// Input Port(s)
input a, b, hourset, s1, s2, s3, s4, dimmer, timeroutoff, blanking, ac, c800hz, c10hz;

// Output Port(s)
output ce, reset, preset, load, duty, strobe, blankingout, acout, timmadj, timhadj;
output [2:0] cs;

// Inout Port(s)

// Parameter Declaration(s)

// Additional Module Item(s)

endmodule

ct.v: CLOCK TIMERモジュール

module ct(ac, cs, timmadj, timhadj, c10hz, c1hz,
clcounter, ontimer, offtimer, sleeptimer, oncmpout, offcmpout, sleepout);

// Input Port(s)
input ac, timmadj, timhadj, c10hz, c1hz;
input [2:0] cs;

// Output Port(s)
output oncmpout, offcmpout, sleepout;
output [16:0] clcounter, ontimer, offtimer, sleeptimer;

// Inout Port(s)

// Parameter Declaration(s)

// Additional Module Item(s)

endmodule

disp.v: DISPLAYモジュール

module disp(c3200hz, cs, fcounter, clcounter, ontimer, offtimer, sleeptimer,
oncmpout, offcmpout, sleep, duty, strobe, ac, blanking,
stopwatch, ambcout, pmfmout, sega, segb, segc, segd, sege, segf, segg, point,
io, signalout, timerout, sleepout);

// Input Port(s)
input c3200hz, oncmpout, offcmpout, sleep, duty, strobe, ac, blanking;
input [2:0] cs;
input [19:0] fcounter;
input [16:0] clcounter, ontimer, offtimer, sleeptimer;

// Output Port(s)
output stopwatch, ambcout, pmfmout, sega, segb, segc, segd, sege, segf, segg, point, signalout, timerout, sleepout;
output [4:0] io;

// Inout Port(s)

// Parameter Declaration(s)

// Additional Module Item(s)

endmodule

ここまで入力している間にもっとインタフェース信号数を減らせることに気づく。それはまた後日検討しよう。

RTLスケルトンをコンパイルしてRTL Viewerでトップブロックを表示すると



もう出来た気分（´ー｀　）

あとは各ブロックの中身のRTLを記述すればよい。